FS2公司的OCI技術可提供深度的、針對SoC內部工作的、覆蓋整個系統的能見度，是實現成功設計和加速上市的關鍵。FS2從1999年起就與MIPS Technologies及其客戶密切合作，針對MIPS-Based(tm)核心，開發尖端的系統除錯與程式追蹤技術。這項合作關係後來更延伸至PDtrace(tm)（Program and Data Trace）晶片內部與外部的追蹤系統開發，並套用在MIPS32(r) 4KE(tm)、MIPS32 24K(r)、以及MIPS32 24KE(tm)等系列的處理器核心。
HT80C51 and HT80C51MX Clockless Microcontroller Cores
支持CPU: HT80C51 和 HT80C51MX
兼容開發環境：Keil 系列
System Navigator for Mentor M8051EW
System Navigator tools for Mentor M8051EW
Synthesizable Microcontroller Cores
System Navigator for Philips LPC952
System Navigator for
Philips LPC952 Microcontroller
ISA-JAZZ System Analyzer
In-Target System Analyzer for Improv Systems Jazz DSP Processor Cores
The ISA-JAZZ In-Target System Analyzer is designed to support the special features and integrated peripherals of the Jazz processor family. It works with the Improv Systems Jazz Standard Tool Suite and provides a JTAG interface to the family DSP processors.
The ISA-Jazz System Analyzer supports JTAG-based debugging for Improv Systems Jazz cores with COOL-Jazz debugging extensions. It features complete run control over one or more Jazz DSP processor cores and enables you to access and modify registers, memory, and I/O. The JTAG based probe works with the Improv Systems tool suite debugger for a graphical user interface. This provides a powerful multi core debug tool for Jazz cores with advanced features at a competitive price.
Key Features
· Read-write all processor registers, memory, and I/O ports
· Go and halt processor run control
· Single step by assembly or C source instruction
· Set hardware and software breakpoints
· Load binary, hex, S-records file formats
· Supports multiple Jazz cores on JTAG chain
· Supports flash programming
· Trigger-in/out signals
· Supported by Jazz debugger and development tool suite
ISA-ZSP500
In-Target System Analyzer for LSI Logic ZSP500 DSP Core
The In-Target System Analyzer supports the LSI Logic ZSP™500 synthesizable DSP core. To learn more about the ZSP500 core, visit the web site at www.zsp.comThe ZSP500 core is available with optional FS2 On-chip Instrumentation (OCI®) IP with trace and triggering features for faster system debug and testing. It provides unique performance analysis features that make it easier to find execution bottlenecks and improve performance.
The FS2 system analyzer probe connects to the ZSP500 target system using a 14-pin JTAG connector or 38-pin Mictor cable (with off-chip trace system). The system runs on a Windows®98/NT/2000/XP PC over an IEEE-1284 EPP/bi-directional parallel port.
Key Features
· Supports LSI Logic ZSP500 DSP core
· Features FS2 On-Chip Instrumentation (OCI) technology
· On-chip trace (standard), off-chip trace, or both
· Supports 24-bit addressing
· Real-time PC execution trace
· Load/store address trace
· Detailed Execution Profiling Trace mode for measuring CPU resource utilization
· Point-to-point timing to assist in code performance optimization
· Trace can be gated on/off by on-chip triggers
· Scalable internal trace depth
· External trace port width and speed selectable
· Max trace depth: on-chip 1024 x 64-bit words, off-chip 64K x 64-bit words
· Unlimited software breakpoints
· ZSP hardware breakpoints
· Go, halt processor run control
· Read-write all general registers and control registers
· Supports multiple cores and mixed RISC/DSP development
· Host binary software interface adheres to MDI specification
· Command-line interface window with Tcl scripting
Sitka Development Board
Evaluation and Development Board for Synopsys DesignWare PCI Express IP
The Sitka development and evaluation board was jointly developed by Synopsys and First Silicon Solutions for the Synopsys DesignWare PCI Express IP. The board functions as a standard PCIe add-in card for systems running either the Windows or Linux operating systems.
The Sitka board contains two large Xilinx Virtex-4 FPGA's which allow you to combine your design with the DesignWare PCI Express IP enabling you to test and debug your PCI Express application in hardware. The FPGA's support partitioning of large designs by providing 272 I/O pins between the two FPGA's. These I/O's can be configured for operation up to 1Gpbs point-to-point to provide high throughput data transfers or grouped into sets of unidirectional channels. The FPGA's are configured with on-board ROM that can hold two or more configurations depending on the bitfile compression that is used.
The board enables testing the DesignWare PCI Express IP with multiple PHYs for maximum flexibility in choosing the PHY for the final design. For testing purposes, you can use the built-in FX60 PHY connecting directly to specific connectors like the PCIe interface and SATA drives or through the 360-pin expansion connector. In addition to using the built-in FPGA PHYs, you can use daughter cards connected to the Sitka board via two different connector locations, including the PCI Express Standard PIPE_C (PHY Interface PCI Express Architecture Connector). The Sikta board can run any combination or all of these interfaces simultaneously.
The Sitka board, when used in conjunction with the industry standard DesignWare PCI Express IP enables faster and easier verification of the design in hardware.
Key Features
· PCIe x8 board edge connector (adaptors plug into a PCIe x1 or x4 PC slot)
· PCI Express PHY Interface for PCI Express Architecture Connector (PIPE_C) enables PHY testing through a PHY daughter card
· PMA Interface connector for use with Synopsys PHY daughter cards
· 2 SATA drive connectors
· 2 SFP connector sites for Gigabit Ethernet (GigE)
· 2 XENPAK connector sites for XAUI (adaptors for additional SATA or SFP)
· Cup connectors for TI power source modules
· 2 Xilinx JTAG connectors, one each wired to FX60 and LX100 for using the ChipScope Pro debugger
In-Target System Analyzer for ZiLOG eZ80 Processor Family
The ISA-eZ80 In-Target System Analyzer is designed to support the special features and integrated peripherals of the eZ80 processor family. It supports the ZiLOG Developer Studio (ZDS) and is integrated with the IAR Embedded Workbench software tools to maximize your productivity.
The system analyzer features complete run control over the eZ80 processor and enables you to access and modify CPU registers, memory, and I/O. FS2's On-Chip Instrumentation (OCI(TM)) debug features built-in to the ZiLOG processors allow FS2 to provide a powerful debug tool with advanced features at a competitive price.
The ISA-eZ80 debugger hardware is contained in a compact chassis that connects to the target system using a 14-pin JTAG connector. The system runs on a Windows® 98/NT/2000 PC over an IEEE-1284 EPP/ECP high-speed parallel port or USB port. The JTAG target interface and high-speed parallel host intface provides typical 8K bytes/sec. loading speeds so you spend more time debugging than waiting for programs to load. A graphical, source level debugger program provides an intuitive, easy to use interface for use with the ZiLOG Developer Studio (ZDS) tools. The system can also be used with the IAR Embedded Workbench debugger interface (sold separately) for complete compatibility with IAR software tools.
IAR Embedded Workbench Interface
IAR Web site
Zilog Web site
Key Features
· Supports ZiLOG eZ80L92, eZ80F91, eZ80F92, eZ80F93, and other processors with available JTAG debug interface
· Read-write all processor registers, memory, and I/O
· Go and halt processor run control
· Trace window with executed assembly and source code
· Single step by assembly or C source instruction
· Unlimited software breakpoints
· Load binary, hex, S-records or COFF (from ZDS) and IAR file formats
· JTAG target and EPP parallel host interface for faster loading
· Flash programming support
· 4 hardware execution breakpoints
· 4 ZDI triggers monitor addrss, address ranges, with option to break on any cycle type
· 4 additional advanced hardware triggers on address, data value, and cycle types, with ranges and masking supported
· Trigger-in/out signals
· Single line assembler and disassembler
· Load code and debug symbols including code, variables, and variable types
· Source level debug from IAR Embedded Workbench interface
FLASH PRO OEM product for Actel ProASIC and ProASICPLUS devices
FPGAView™ Software
Software for Configuring and Debugging Altera and Xilinx FPGA Devices with Tektronix Logic Analyzers
The FPGAView™ software is a PC Windows-based program
FS2 BUS NAVIGATOR™
On-chip FS2 Bus Navigator™ Solutions for AMBA, OCP,
and Sonics SiliconBackplane Bus Systems
The FS2 Bus Navigator™ is used for monitoring signal activity and for debugging complex bus/system interactions in System-on-Chip designs. It allows the user to capture bus activity in real-time and display critical information for analysis on a host PC.
The system consists of an On-chip Instrumentation (OCI®) synthesizable logic block, a JTAG hardware probe, and PC based software for controlling probing and analysis. The OCI passively captures bus activity, buffers it using on-chip RAM, and transfers the collected data off-chip via a JTAG port to the external JTAG probe. The host PC controls the trace collection process and provides captured bus history to the user with an easy-to-use graphical interface. The system runs on a Windows® 2000/XP PC over a USB 2.0 or optional 10/100 Ethernet port. It provides a comprehensive debug tool for complex SoC bus designs at a competitive price.
Key Features
· Captures bus activity in real-time
· Available for AMBA, OCP, and Sonics SiliconBackplane buses
· Captures bus signals and additional user-defined inputs attached to other nodes in the SOC
· Bus clock mode trace stores signals on every clock
· Bus transfer mode aligns bus transfers and response phases for single event triggering using combinations of address, data, and control
· Filtering of wait and idle state cycles in bus transfer mode
· Trace storage qualifiers; single cycle, start or stop trace on any trigger, counter, and state sequencer condition
· Configurable for user defined number of Masters
· Trace buffer stores bus cycles or bus transfers based on RAM memory size
· Up to 16 user defined triggers recognize combinations of 1, 0, X, signal values
· Sequential event monitoring using cascadable trigger states (2 to 16 states)
· Two 32-bit event counter/timers
· Trigger conditions include bus and user defined signals, Event counter/timer value, and Trigger state
· Actions include Trigger, Trace control (start, stop, single), Trig Out control (pulse, assert, negate), Counter control (increment, start, stop, clear), and Goto state
· Trigger position variable in 1/512 increments of trace depth
· User difinable timestamp records duration of each trace frame from the start of trace, displayable as absolute or delta times
· Automatic trace clock frequency measurement allows displaying frame durations in either nanoseconds or clocks
· Multiple external trigger in/out with configurable logic levels
· Easy-to-use graphical software interface with state views and waveform views of data
· Symbolic lookup and signal value naming support for ease of viewing and analysis
· Optional VCD format export for integration with simulation environments
Cadence Emulation Tools Support
Integrating Instrumentation Tools into System-Level Verification Flows. This is a PowerPoint presentation.
