1999年和2004年分別在清華電子工程系和微電子所獲得學士和博士學位。2004年留校任教，2006年、2013年和2017年分別在歐洲微電子中心、美國麻省理工學院和英國牛津大學學術訪問。現為清華微電子所長聘教授（Tenured Prof.），博士生導師，同時擔任清華大學硬體安全和密碼晶片實驗室主任、清華大學移動計算研究中心副主任。長期從事可重構計算及其晶片、硬體安全和密碼晶片等關鍵技術研究。先後主持863計畫重點項目（首席專家）、國家自然科學基金重點項目（總負責人）、“核高基”重大專項課題（總負責人）、國防科工局基礎研究項目、國際合作重大項目等20餘個項目。發表SCI索引論文100餘篇（IEEE Transactions論文50餘篇）、EI索引論文60餘篇（ISCA/DAC等頂級會議論文20餘篇），授權發明專利60餘項，出版著作5部、譯作4部。歷任亞洲固態電路會議IEEE A-SSCC的組委會主席/副主席、TPC副主席、TPC委員等；電子設計自動化領域頂級會議DAC的TPC委員；IEEE CAS VSPC的TC委員；中國密碼學會密碼晶片專委會副主任委員、秘書長。所突破的關鍵技術在信息安全晶片、可程式器件、可穿戴計算晶片和CPU晶片加速器等領域取得套用。獲國家技術發明二等獎、中國專利金獎、教育部技術發明一等獎、江西省科技進步二等獎等科技獎勵。
獨立主持4門課程，獲清華大學本科生精品課、北京市青年教師教學競賽一等獎、清華大學青年教師教學競賽一等獎、清華大學青年教師教學優勝獎、MOOC教學先鋒獎等多個教學獎勵。
基本介紹
- 中文名：劉雷波
- 職業：清華微電子所長聘教授
- 畢業院校：清華大學
承擔科研項目,所授課程,個人榮譽,社會兼職,學術專著,近5年代表性論文,
承擔科研項目
2019年-2023年，承擔自然科學基金重點項目“動態可重構晶片關鍵技術”（項目總負責人）
2018年-2019年，承擔“核高基”重大專項課題“面向伺服器CPU熔斷和幽靈等硬體安全威脅的硬體檢測方案設計及晶片驗證”（課題總負責人）
2017年-2020年，承擔自然科學基金面上項目“動態局部重構密碼晶片抗物理攻擊關鍵技術研究”（項目負責人）
2016年-2018年，承擔英特爾國際合作重大項目“融合可重構計算和英特爾X86架構技術的新型通用CPU”（項目負責人）
2012年-2016年，承擔“十二五”863計畫重點項目“面向通用計算的可重構處理器關鍵技術研發”（項目首席專家）
2009年-2012年，“十一五”863計畫重點項目子課題“可重構PE和PE陣列的架構設計和IP核實現”（子課題負責人）
所授課程
積體電路集成I（英文授課），課程號：30260163，本科生必修課，2018年起每個秋季學期授課
數字積體電路設計與分析（英文授課），課程號：40260173，本科生必修課，2005年起每個秋季學期授課
VLSI數位訊號處理，課程號：81020082，研究所選修課，2006-2012年，2017-至今，每個春季學期授課
數字積體電路設計與分析（英文授課），大規模線上課程（慕課），2015年秋季學期開始授課
個人榮譽
科研方面
2018年，研究成果被世界網際網路大會評為全球領先科技成果
2018年，獲中國電子學會“優秀科技工作者”稱號
2017年，獲中國發明協會發明創業獎·人物獎
2015年，獲國家技術發明二等獎（第2完成人）
2015年，獲中國專利金獎（第1完成人）
2014年，獲教育部技術發明一等獎（第3完成人）
2014年，獲江西省科技進步二等獎（第4完成人）
教學方面
2016年，獲MOOC教學先鋒獎
2012年，獲清華大學教學成果獎二等獎
2011年，獲第七屆北京青年教師教學基本功比賽一等獎
2011年，獲得廖凱原獎教金
2010年，獲清華大學青年教師教學優秀獎（清華面向青年教師設立的教學最高獎）
2010年，獲清華大學第四屆青年教師教學大賽一等獎
此外，自2010年起主持清華大學本科生精品課程“數字積體電路分析與設計”
社會兼職
IEEE A-SSCC (IEEE亞洲固態電路國際會議)
2008年~至今，任IEEE A-SSCC (亞洲固態電路會議)技術委員會 (TPC) 成員；
2016年，任IEEE A-SSCC (亞洲固態電路會議) STGA (Student TravelGrant Award) 分委會主席；
2015年，任IEEE A-SSCC (亞洲固態電路會議) 大會組委會主席；
2013年，任IEEE A-SSCC (亞洲固態電路會議) 技術委員會副主席。
DAC（電子設計自動化會議）
2017年~至今，任DAC(電子設計自動化會議) 技術委員會 (TPC) 成員。
IEEE CAS VSPC (IEEE電路系統學會視頻信號處理與通訊協會)
2016年~至今，任IEEE CAS VSPC(視頻信號處理與通訊協會)技術委員會 (TC) 成員。
中國密碼學會密碼晶片專業委員會
2018年~至今，任中國密碼學會密碼晶片專業委員會副主任委員，秘書長。
中國工程院院刊-信息與電子工程前沿（“Frontiers of Information Technology & Electronic Engineering”，英文期刊）
2019年~至今，擔任該期刊執行副主編，SCI 源刊。
學術專著
2019年，《大規模MIMO 檢測算法VLSI架構——專用電路及動態重構實現》，科學出版社，作者：劉雷波、彭貴強、魏少軍
2019年，《Massive MIMO Detection Algorithm and VLSI Architecture》，Springer出版社，作者：Leibo Liu、Guiqiang Peng、Shaojun Wei
2018年，《Reconfigurable Cryptographic Processor》，Springer出版社，作者：Leibo Liu、Bo Wang、Shaojun Wei
2018年，《Approximate Arithmetic Circuits: Design and Evaluation》，Springer出版社，參與撰寫第一章
2018年，《積體電路產業全書》，電子工業出版社，參與撰寫第十章
2017年，《可重構計算密碼處理器》，科學出版社，作者：劉雷波、王博、魏少軍
2014年，《可重構計算》，科學出版社，作者：魏少軍、劉雷波、尹首一
近5年代表性論文
*表示為通訊作者；姓名斜體表示為指導的學生。
期刊論文：
L. Liu, B. Wang, C. Deng, M. Zhu, S. Yin, S. Wei. “Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD), DOI：10.1109/TCAD.2018.2801229.
L. Liu, Q. Wang, W. Zhu, H. Mo, T. Wang, S. Yin, Y. Shi, S. Wei, “ A Face Alignment Accelerator Based on Optimized Coarse-to-Fine Shape Searching,”IEEE Transactions on Circuits and Systems for Video Technology(TCSVT), DOI: 10.1109/TCSVT.2018.2867499.
Liu L, Zhu W, Yin S, et al. “A Binary-Feature-Based Object Recognition Accelerator with 22 M-Vector/s Throughput and 0.68 G-Vector/J Energy-Efficiency for Full-HD Resolution,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD), DOI:10.1109/TCAD. 2018.2846634.
G. Peng,*L. Liu, S. Zhou, Y. Xue, S. Yin, S. Wei, “Algorithm and Architecture of a Low-Complexity and High-Parallelism Preprocessing-Based K-Best Detector for Large-Scale MIMO Systems,”IEEE Transactions on Signal Processing (TSP), DOI:10.1109/TSP.2018.2799191.
H. Huang,*L. Liu,Q. Huang, Y. Chen, S. Yin, S. Wei. " Low Area-Overhead Low-Entropy Masking Scheme (LEMS) Against Correlation Power Analysis Attack,"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD)，2018. DOI: 10.1109/TCAD.2018.2802867.
Y. Lu,*L. Liu, Y. Deng, J. Weng, S. Yin, Y. Shi and S. Wei. “ Triggered-Issuance and Triggered-Execution: A Control Paradigm to Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained Reconfigurable Arrays,”IEEE Transactions on Parallel and Distributed Systems(TPDS), DOI: 10.1109/TPDS.2018.2822708.
H. Mo,*L. Liu, W. Zhu, S. Yin, S. Wei, “ Face Alignment with Expression- and Pose-Based Adaptive Initialization,”IEEE Transactions on Multimedia, 2018, DOI: 10.1109/TMM.2018.2867262.
L. Wang, P. Lv,*L. Liu, et al. "A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems,"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD), DOI: 10.1109/TCAD.2018.2855168.
Z. Li, *L. Liu, Y. Deng, S. Yin, S. Wei. “ Breaking the Synchronization Bottleneck with Reconfigurable Transactional Execution,” IEEE Computer Architecture Letters, DOI: 10.1109/LCA.2018.2828402.
L. Liu, C. Yang, S. Yin, S. Wei, “CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 37, no. 6, pp. 1171 - 1184, June 2018. DOI: 10.1109/TCAD.2017.2748026.
L. Liu, Z. Zhou, S. Wei, M. Zhu, S. Yin, S. Mao, “DRMaSV: Enhanced Capability against Hardware Trojans in Coarse Grained Reconfigurable Architectures,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017. DOI: 10.1109/TCAD.2017.2729340.
L. Liu, Z. Li, C. Yang, C. Deng, S. Yin, S. Wei, “HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric for 13-Dwarfs Processing,”IEEE Transactions on Circuits and Systems II: Express Briefs（TCAS-II）,2017. DOI: 10.1109/TCSII.2017.2728814.
G. Peng, *L. Liu, S. Zhou, S. Yin, S. Wei, “A 1.58 Gbps/W 0.40 Gbps/mm2 ASIC Implementation of MMSE Detection for 128*8 64-QAM Massive MIMO in 65 nm CMOS,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS- I), 2017.DOI: 10.1109/TCSI.2017.2754282.
G. Peng, *L. Liu, P. Zhang, S. Yin, S. Wei, “Low-Computing-Load, High-Parallelism Detection Method based on Chebyshev Iteration for Massive MIMO Systems with VLSI Architecture,” IEEE Transactions on Signal Processing (TSP),vol. 65,no. 14, pp. 3775-3788, April 2017. DOI: 10.1109/TSP.2017.2698410.
C. Wu, C. Deng, *L. Liu, J. Han, J. Chen, S. Yin, S. Wei, “A Multi-Objective Model Oriented Mapping Approach for NoC-based Computing Systems,” IEEE Transactions on Parallel and Distributed Systems(TPDS), vol. 28, no. 3, pp. 662-676，March 2017. DOI: 10.1109/TPDS.2016.2589934.
B. Wang, *L. Liu, C. Deng, M. Zhu, S. Yin, Z. Zhou, S. Wei, “Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks,” IEEE Transactions on Information Forensics and Security (TIFS), vol. 12, no. 2, pp. 309-322, Feb. 2017. DOI: 10.1109/TIFS.2016.2612638.
C. Yang,*L. Liu, K. Luo, S. Yin, S. Wei, “CIACP: A Correlation- and Iteration-Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays,”IEEE Transactions on Parallel and Distributed Systems(TPDS), vol. 28, no. 1, pp. 29-43, January 2017. DOI: 10.1109/TPDS.2016.2554278.
C. Deng, *L. liu, Y. Liu, S. Yin, S. Wei, “PMCC: Fast and Accurate System-Level Power Modeling for Processors on Heterogeneous SoC,” IEEE Transactions on Circuits and Systems II: Express Briefs（TCAS-II）, vol. 64, no. 5, pp. 540-544, May 2017, DOI: 10.1109/TCSII.2016.2615930.
L. Liu, J. Wang, J. Zhu, C. Deng, S. Yin, S. Wei, “TLIA: Efficient Reconfigurable Architecture for Control-Intensive Kernels with Triggered-Long-Instructions,” IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 27, no. 7, pp. 2143-2154, 2016. DOI: 10.1109/TPDS.2015.2477841.
B. Wang, *L. Liu, C. Deng, M. Zhu, S. Yin, S. Wei, “Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture,” IEEE Transactions on Information Forensics and Security (TIFS), vol. 11, no. 6, pp. 1151-1164, 2016. DOI: 10.1109/TIFS.2016.2518130.
W. Zhu, *L. Liu, G. Jiang, S. Yin, S. Wei, “A 135 fps 1080p 87.5 mW Binary Descriptor Based Image Feature Extraction Accelerator,” IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), vol. 26, no. 8, pp. 1532-1543, 2016. DOI: 10.1109/TCSVT.2015.2469116.
L. Liu, D. Wang, M. Zhu, Y. Wang, S. Yin, P. Cao, J. Yang, S. Wei, “An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding,” IEEE Transactions on Multimedia (TMM), vol. 17, no. 10, pp. 1706-1720, 2015. DOI: 10.1109/TMM.2015.2463735.
L. Liu, C. Wu, C. Deng, S. Yin, Q. Wu, J. Han, S. Wei, “A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 23, no. 11, pp. 2566-2580, 2015. DOI: 10.1109/TVLSI.2014.2367108.
C. Wu, C. Deng, *L. Liu, J. Han, J. Chen, S. Yin, S. Wei, “An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 8, pp. 1264-1277, 2015. DOI: 10.1109/TCAD.2015.2422843.
J. Zhu, *L. Liu, S. Yin, X. Yang, S. Wei, “A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 23, no. 9, pp. 1700-1709, 2015. DOI: 10.1109/TVLSI.2014.2349652.
L. Liu, D. Wang, S. Yin, Y. Chen, M. Zhu, S. Wei, “SimRPU: A Simulation Environment for Reconfigurable Architecture Exploration,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 22, no. 12, pp. 2635-2648, 2014. DOI: 10.1109/TVLSI.2013.2295622.
L. Liu, W. Zhu, S. Yin, E. Y. Tang, P. Peng, “An uneven-dual-core processor based mobile platform for facilitating the collaboration among various embedded electronic devices,” IEEE Transactions on Consumer Electronics (TCE), vol. 60, no. 1, pp. 137-145, 2014. DOI: 10.1109/TCE.2014.6780936.
J. Zhu, *L. Liu, S. Yin, S. Wei, “Low-Power Reconfigurable Processor Utilizing Variable Dual VDD,” IEEE Transactions on Circuits and Systems II. Express Briefs (TCAS-II), vol. 60, no. 4, pp. 217-221, 2013. DOI: 10.1109/TCSII.2013.2251940.
Y. Wang, *L. Liu, S. Yin, M. Zhu, P. Cao, J. Yang, S. Wei, “On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 22, no. 5, pp. 983-994, 2014. DOI: 10.1109/TVLSI.2013.2263155.
會議論文：
L. Liu, A. Luo, G. Li, J. Zhu, Y. Wang, G. Shan, J. Pan, S. Yin, S. Wei. “Jintide: A Hardware Security Enhanced Server CPU with Xeon Cores under Runtime Surveillance by an In-Package Dynamically Reconfigurable Computing Processor”. 31st Hot Chips: A Symposium on High Performance Chips( Hot Chips 2019), Stanford, Palo Alto, CA, USA, 18-20, August, 2019(Accepted)
X. Man, *L. Liu, J. Zhu, S. Wei. “A General Pattern-Based Dynamic Compilation Framework for Coarse-Grained Reconfigurable Architectures”. 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC), Las Vegas, Nevada, USA, 2-7, June 2019, 1- 6(Accepted)
H. Mo, *L. Liu, W. Zhu, Q. Li, H. Liu, W. Hu, Y. Wang, S. Wei. “A 1.17 TOPS/W, 150fps Accelerator for Multi-Face Detection and Alignment”. 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC), Las Vegas, Nevada, USA, 2-7, June 2019, 1- 6(Accepted)
H. Liu, *L. Liu, W. Zhu, Q. Li, H. Mo, S. Wei. “L-MPC: A LUT based Multi-Level Prediction-Correction Architecture for Accelerating Binary-Weight Hourglass Network”. 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC), Las Vegas, Nevada, USA, 2-7, June 2019, 1-6(Accepted)
Z. Li,*L. Liu, Y. Deng, S. Yin, Y. Wang, S. Wei, “Aggressive Parallelization of Irregular Applications on Reconfigurable Hardware,”in the 44thInternational Symposium on Computer Architecture (ISCA), Toronto, Canada ,June，2017, pp. 575-586. DOI: 10.1145/3140659.3080228
Q. Wang,*L. Liu, W. Zhu, H. Mo, C. Deng, S. Wei, “A 700fps Optimized Coarse-to-Fine Shape Searching Based Hardware Accelerator for Face Alignment,”in the 54th Annual Design Automation Conference (DAC 2017),Austin, TX, USA, June 2017, pp.57-57.DOI: 10.1145/3061639.3062182[Best Paper Nomination].
G. Peng, *L. Liu, Q. Wei, Y. Wang, S. Yin, S. Wei. “A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128*8 Massive MIMO Systems”, IEEE Asian Solid-State Circuits Conference (A-SSCC 2018), Tainan, Taiwan, 5-7 November.
Y. Lu,*L. Liu, Y. Deng, J. Weng, Z. Li, C. Deng and S. Wei, “Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution,”inthe 54th Annual Design Automation Conference (DAC 2017), Austin, TX, USA, June, 2017, pp.71-71. DOI: 10.1145/3061639.3062284.
C. Yang, *L. Liu, S. Yin, and S. Wei, “Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays,” in the 53rd Annual Design Automation Conference (DAC 2016), Austin, TX, United States, June， 2016, pp. 1-6. DOI: 10.1145/2897937.2898001.
J. Wang,*L. Liu, J. Zhu, S. Yin, S. Wei, “Acceleration of control flows on Reconfigurable Architecture with a composite method,”inthe 52rd Annual Design Automation Conference(DAC 2015), San Francisco, CA, USA, Jun. 2015, pp. 1-6, DOI: 10.1145/2744769.2744789.
G. Jiang, *L. Liu, W. Zhu, S. Yin, S. Wei, “A 127 fps in full HD accelerator based on optimized AKAZE with efficiency and effectiveness for image feature extraction,” in the 52rd Annual Design Automation Conference(DAC 2015), San Francisco, CA, USA, Jun. 2015, pp. 1-6. DOI:10.1145/2744769.2744772
L. Liu, Y. Ren, C. Deng, S. Yin, S. Wei, J. Han, “A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures,” in the 2015 20st Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba, Japan, Jan. 2015, pp. 48-53, DOI: 10.1109/ASPDAC.2015.7058980.
