David A.Patterson 加州大學伯克利分校計算機科學系教授，美國國家工程研究院院士，IEEE和ACM會士，曾因成功的啟發式教育方法被IEEE授予James H. Mulligan，Jr教育獎章。他因為對RISC技術的貢獻而榮獲1995年IEEE技術成就獎，而在RAID技術方面的成就為他贏得了1999年IEEE ReynoldJohnson信息存儲獎。2000年他和John L. Hennessy分享了John vonNeumann獎。
John L.Hennessy 史丹福大學校長，IEEE和ACM會士，美國國家工程研究院院士及美國科學藝術研究院院士。Hennessy教授因為在RISC技術方面做出了突出貢獻而榮獲2001年的Eckert-Mauchly獎章，他也是2001年Seymour Cray計算機工程獎得主，並且和David A.Patterson分享了2000年John von Neumann獎。
1 computer abstractions and technology 2 1.1 introduction 3 1.2 belowyour program 10 1.3 under the covers 13 1.4 performance 26 1.5 the power wall 39 1.6 the sea change: the switch from uniprocessors to multiprocessors 41 1.7 real stuff: manufacturing and benchmarking the amd opteron x4 44 1.8 fallacies and pitfalls 51 1.9 concluding remarks 54 1.10 historical perspective and further reading 55 1.11 exercises 56 2 instructions: language of the computer 74 2.1 introduction 76 2.2 operations of the computer hardware 77 2.3 operands of the computer hardware 80 2.4 signed and unsigned numbers 87 2.5 representing instructions in the computer 94 2.6 logical operations 102 .2.7 instructions for making decisions 105 2.8 supporting procedures in computer hardware 112 2.9 communicating with people 122 2.10 mips addressing for 32-bit immediates and addresses 128 2.11 parallelism and instructions: synchronization 137 2.12 translating and starting a program 139 2.13 a c sort example to put it all together 149 2.14 arrays versus pointers 157 2.15 advanced material: compiling c and interpreting java 2.16 real stuff: arm instructions 161 2.17 real stuff: x86 instructions 165 2.18 fallacies and pitfalls 174 2.19 concluding remarks 176 2.20 historical perspective and further reading 179 2.21 exercises 179 3 arithmetic for computers 222 3.1 introduction 224 3.2 addition and subtraction 224 3.3 multiplication 230 3.4 division 236 3.5 floating point 242 3.6 parallelism and computer arithmetic: associativity 270 3.7 real stuff: floating point in the x86 272 3.8 fallacies and pitfalls 275 3.9 concluding remarks 280 3.10 historical perspective and further reading 283 3.11 exercises 283 4 the processor 298 4.1 introduction 300 4.2 logic design conventions 303 4.3 building a datapath 307 4.4 a simple implementation scheme 316 4.5 an overview of pipelining 330 4.6 pipelined datapath and control 344 4.7 data hazards: forwarding versus stalling 363 4.8 control hazards 375 4.9 exceptions 384 4.10 parallelism and advanced instruction-level parallelism 391 4.11 real stuff: the amd opteron x4 (barcelona) pipeline 404 4.12 advanced topic: an introduction to digital design using a hardware design language to describe and model a pipeline and more pipelining illustrations 406 4.13 fallacies and pitfalls 407 4.14 concluding remarks 408 4.15 historical perspective and further reading 409 4.16 exercises 409 5 large and fast: exploiting memory hierarchy 450 5.1 introduction 452 5.2 the basics of caches 457 5.3 measuring and improving cache performance 475 5.4 virtual memory 492 5.5 a common framework for memory hierarchies 518 5.6 virtual machines 525 5.7 using a finite-state machine to control a simple cache 529 5.8 parallelism and memory hierarchies: cache coherence 534 5.9 advanced material: implementing cache controllers 538 5.10 real stuff: the amd opteron x4 (barcelona) and intel nehalem memory hierarchies 539 5.11 fallacies and pitfalls 543 5.12 concluding remarks 547 5.13 historical perspective and further reading 548 5.14 exercises 548 6 storage and other i/0 topics 568 6.1 introduction 570 6.2 dependability, reliability, and availability 573 6.3 disk storage 575 6.4 flash storage 580 6.5 connecting processors, memory, and i/o devices 582 6.6 interfacing i/o devices to the processor, memory, and operating system 586 6.7 i/o performance measures: examples from disk and file systems 596 6.8 designing an i/o system 598 6.9 parallelism and i/o: redundant arrays of inexpensive disks 599 6.10 real stuff: sun fire x4150 server 606 6.11 advanced topics: networks 612 6.12 fallacies and pitfalls 613 6.13 concluding remarks 617 6.14 historical perspective and further reading 618 6.15 exercises 619 7 multicores, muluprocessors, and clusters 630 7.1 introduction 632 7.2 the difficulty of creating parallel processing programs 634 7.3 shared memory multiprocessors 638 7.4 clusters and other message-passing multiprocessors 641 7.5 hardware multithreading 645 7.6 sisd, mimd, simd, spmd, and vector 648 7.7 introduction to graphics processing units 654 7.8 introduction to multiprocessor network topologies 660 7.9 multiprocessor benchmarks 664 7.10 roofiine: a simple performance model 667 7.11 real stuff: benchmarking four multicores using the roofline model 675 7.12 fallacies and pitfalls 684 7.13 concluding remarks 686 7.14 historical perspective and further reading 688 7.15 exercises 688 appendices a graphics and computing gpus a-2 a.1 introduction a-3 a.2 gpu system architectures a-7 a.3 programming gpus a-12 a.4 multithreaded multiprocessor architecture a-25 a.5 parallel memory system a-36 a.6 floating point arithmetic a-41 a.7 real stuff: the nvidia geforce 8800 a-46 a.8 real stuff: mapping applications to gpus a-55 a.9 fallacies and pitfalls a-72 a.10 concluding remarks a-76 a.11 historical perspective and further reading a-77 b assemblers, linkers, and the spim simulator b.1 introduction b-3 b.2 assemblers b-10 b.3 linkers b-18 b.4 loading b-19 b.5 memory usage b-20 b.6 procedure call convention b-22 b.7 exceptions and interrupts b-33 b.8 input and output b-38 b.9 spim b-40 b.10 mips r2000 assembly language b-45 b.11 concluding remarks b-81 b.12 exercises b-82 index i-1 cd-rom content c the basics of logic design c-2 c.1 introduction c-3 c.2 gates, truth tables, and logic equations c-4 c.3 combinational logic c-9 c.4 using a hardware description language c-20 c.5 constructing a basic arithmetic logic unit c-26 c.6 faster addition: carry lookahead c-38 c.7 clocks c-48 c.8 memory elements: flip-flops, latches, and registers c-50 c.9 memory elements: srams and drams c-58 c.10 finite-state machines c-67 c.11 timing methodologies c-72 c.12 field programmable devices c-78 c.13 concluding remarks c-79 c.14 exercises c-80 d mapping control to hardware d-2 d.1 introduction d-3 d.2 implementing combinational control units d-4 d.3 implementing finite-state machine control d-8 d.4 implementing the next-state function with a sequencer d-22 d.5 translating a microprogram to hardware d-28 d.6 concluding remarks d-32 d.7 exercises d-33 e a survey of risc architectures for desktop,server, and embedded computers e-2 e.1 introduction e-3 e.2 addressing modes and instruction formats e-5 e.3 instructions: the mips core subset e-9 e.4 instructions: multimedia extensions of the desktop/server riscs e-16 e.5 instructions: digital signal-processing extensions of the embedded riscs e-19 e.6 instructions: common extensions to mips core e-2( e.7 instructions unique to mips-64 e-25 e.8 instructions unique to alpha e-27 e.9 instructions unique to sparc v.9 e-29 e.10 instructions unique to powerpc e-32 e.11 instructions unique to pa-risc 2.0 e-34 e.12 rnstructions unique to arm e-36 e.13 instructions unique to thumb e-38 e.14 instructions unique to superh e-39 e.15 instructions unique to m32r e-40 e.16 instructions unique to mips-16 e-40 e.17 concluding remarks e-43 glossary g-1 further reading fr-1
